Frequently Asked Questions

The Technology:

The Consortium:

The Future of HMC:

The Technology:

  • What is the problem that HMC solves?
    • Over time, memory bandwidth has become a bottleneck to system performance in high-performance computing, high-end servers, graphics, and (very soon) mid-level servers.  Conventional memory technologies are not scaling with Moore's Law; therefore, they are not keeping pace with the increasing performance demands of the latest microprocessor roadmaps.  Microprocessor enablers are doubling cores and threads-per-core to greatly increase performance and workload capabilities by distributing work sets into smaller blocks and distributing them among an increasing number of work elements, i.e. cores.  Having multiple compute elements per processor requires an increasing amount of memory per element.  This results in a greater need for both memory bandwidth and memory density to be tightly coupled to a processor to address these challenges.  The term "memory wall" has been used to describe this dilemma.

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  • Why is the current DRAM technology unable to fully solve this problem?
    • Current memory technology roadmaps do not provide sufficient performance to meet the CPU and GPU memory bandwidth requirements.

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  • What makes HMC so different?
    • HMC represents a fundamental change in memory construction and connectivity.  Utilizing 3D interconnect technology, HMC blends the best of logic and DRAM processes into a heterogeneous package.  At the foundation of HMC is a small logic layer which sits below vertical stacks of DRAM die connected by through-silicon via (TSV) bonds.  An energy optimized DRAM array provides efficient access to memory bits via the logic layer, providing an intelligent memory device truly optimized for performance and energy efficiencies.  This elemental change in how memory is built into a system is paramount.  By placing intelligent memory on the same substrate as the processing unit, each part of the system can do what it's designed to do far more optimally than any previous technology.

      With performance levels that break through the memory wall, Hybrid Memory Cube represents the key to extending network system performance to push through the challenges of new 100G and 400G infrastructure growth.  HMC will also enable exascale CPU system performance growth for next generation HPC systems.

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  • What are the measurable benefits of HMC
    • HMC is a revolutionary innovation in DRAM memory architecture that sets a new standard for memory performance, power, reliability, and cost. This major technology leap breaks through the memory wall, unlocking previously unthinkable processing power and ushering in a new generation of computing.
      • Increased Bandwidth — A single HMC unit can provide more than 15X the bandwidth of a DDR3 module.
      • Reduced Latency – With vastly more responders built into HMC, we expect lower queue delays and higher bank availability, which will provide a substantial system latency reduction.
      • Power Efficiency — The revolutionary architecture of HMC allows for greater power efficiency and energy savings, utilizing 70% less energy per bit than DDR3 DRAM technologies.
      • Smaller Physical Footprint — The stacked architecture uses nearly 90% less physical space than today’s RDIMMs.
      • Pliable to Multiple Platforms — Logic layer flexibility allows HMC to be tailored to multiple platforms and applications.

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  • Many products are touted as green.  What makes HMC stand out as a product that will have a meaningful, positive impact on the environment?
    • This technology requires a small fraction of the energy required to move data as compared to existing memory solutions. The impact that HMC could have on far memory applications is nothing short of remarkable.

      HMC will deliver a significant impact to Total Cost of Ownership (TCO). At 70% energy savings in moving data, HMC will provide large system vendors lower energy profiles for next generation system design.

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  • What does the implementation of HMC look like? What challenges are there with this implementation?
    •  HMC will be tightly coupled with CPUs, GPUs, and ASICS in point-to-point configurations where HMC performance is available for optimal memory bandwidth. Additional implementations will occur in systems using HMC for density improvements, which would be similar to traditional DDR memory implementations.  The only potential early challenge could be that HMC provides far more bandwidth than system implementations can utilize.  

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The Consortium:

  • What is the Hybrid Memory Cube Consortium and what are its goals?
    • The HMCC is a working group made up of industry leaders who build, design in, or enable HMC technology.  The goal of the HMCC is to define an industry adoptable HMC interface and facilitate the integration of HMC into a wide variety of systems, platforms and applications that enables developers, manufacturers, and enablers to leverage this revolutionary technology.
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  • How can my company get involved with the HMC Consortium?
    • Currently HMCC is accepting an unlimited number of Adopters.  Adopters can apply for access to the HMC specification and participate in the specification review, discussion and development.  To learn more about joining the HMCC click here.

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The Future of HMC:

  • Will there be tools available to support the adoption process of HMC?
    • Yes, the mission of the Hybrid Memory Cube Consortium (HMCC) is to facilitate the broad adoption of HMC technology.  The HMCC Web site, hybridmemorycube.org, will provide a wide range of tools and documentation for developers, manufacturers, and enablers.
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  • When will the HMC specification be available?
    • The goal of the consortium is to deliver an industry-adoptable specification in 2012.

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HMCC has delivered the first Draft HMC Specification to Adopters! Be among the first to review by visiting the About Us page and requesting the Adopters Agreement.